Method and apparatus for displaying data on a matrix display with an alternating order of scanning in adjacent groups of columns

ABSTRACT

The present invention relates to a process for displaying data on a matrix display consisting of N data lines and P selection lines at the intersections of which are situated the image points or pixels. The N data lines are grouped into {dot over (P)} blocks if N′ lines where N={grave over (P)}×N′. Each block receives in parallel one of the P′ data signals which is demultiplexed on the N′ lines of the said block. The scanning of the N′ data lines of a block is carried out from 1 to N′ or from N′ to 1, alternately, according to the selection lines.

BACKGROUND OF INVENTION

The present invention relates to a process for displaying data on amatrix display, more particularly a matrix display consisting of N datalines and M selection lines at the intersections of which are situatedimage points or pixels, and in which the N data lines are grouped into Pblocks of N′ data lines each.

Among matrix displays, the liquid crystal screens used in direct viewingmode or in projection mode are in particular known. These screens are,in general, composed of a first substrate comprising selection lines,hereinafter referenced lines, and data lines, hereinafter referencedcolumns, at the intersections of which are situated the image points andof a second substrate comprising a back electrode, the liquid crystalsbeing inserted between the two substrates. The image points consist inparticular of pixel electrodes connected across switching circuits, suchas transistors, to the selection lines and the data lines. The selectionlines and the data lines are respectively connected to peripheralcontrol circuits generally referred to as “drivers”. The line driversscan the lines one after another and close the switching circuits, thatis to say turn on the transistors of each line. On the other hand, thecolumn drivers apply a cue to each data line, that is to say they chargethe electrodes of the selected pixels and modify the optical propertiesof the liquid crystal contained between these electrodes and the backelectrode, thus allowing the formation of images on the screen. When thematrix display comprises a limited number of lines and columns, eachcolumn is connected by its own connection line to the column drivers ofthe screen.

In the case of a screen with high definition, the principle ofmultiplexing is used between the outputs of the column driver and thecolumns of the screen in such a way as to reduce the number of tracks atthe input of the cell. Thus, in French patent application No. 96 00259filed on 11 Jan. 1996 in the name of the Applicant, there is described acolumn control circuit of a matrix display such as represented in FIG.1. In this case, the columns are grouped into P blocks 1 of N′ columns,i.e. 9 columns C1, C2, C3 . . . C9 in the embodiment represented. Eachblock consists of transistors 3, one of the electrodes of which islinked to a column and the other electrode of which is connected to thesame electrode of the other transistors of the block, together theseelectrodes being connected to a video input referenced DB1 for the firstblock, DB2 for the second block, DBP for the last block. The gates ofthe transistors 3 each receive a demultiplexing signal DW1, DW2, DW3 . .. DW9. Each block exhibits the same structure.

The timing diagrams for the voltages read off from the successivecolumns of one and the same block 1 receiving a video signal DB1 to DBPare represented in FIG. 2. In plotting these timing diagrams it has beenassumed that the DC and AC voltage errors introduced bycolumn-line-column coupling (referenced 2 in FIG. 1), the origin ofwhich was described in French patent No. 96 00259 filed on 11 Jan. 1996,are perfectly corrected by the compensation circuit presented in thissame patent. Each timing diagram represents a line time of a givencolumn (1 to 9) of a block connected for example to DB1. In the case ofa line time of 32 μs, the signals can be broken down as follows:

1. Precharging of all the columns of the 4 μs matrix 2. Stabilization ofthe precharge 0.5 μs 3. Sampling of the video over the 9 columns 9 × 2μs of the block DB 4. Equalization between column and pixel 7.5 μs

These diagrams show that the voltage of the columns and hence the RMSvoltage across the terminals of the liquid crystal cell, the electrodesof which are respectively the column and the electrode CE opposite,changes according to the order of sampling of the columns of a blockconnected to DBP. Now, since the dielectric constant of the liquidcrystal varies as a function of the voltage applied to its terminals,the columns of one and the same block receiving a signal DBi do nottherefore exhibit the same charging capacity. Consequently, the couplingbetween the gates of the sampling transistors and the columns of one andthe same block receiving the signal DBi increases as a function of theorder of sampling of the columns, this introducing a DC error of severaltens of mV between the first column sampled in the block receiving thesignal DBi and the last.

The purpose of the present invention is to propose a process fordisplaying data on a matrix display which makes it possible to remedythis drawback.

SUMMARY OF THE INVENTION

Accordingly, the subject of the present invention is a process fordisplaying data on a matrix display consisting of N data lines and Mselection lines at the intersections of which are situated the imagepoints or pixels, and in which the N data lines are grouped into Pblocks of N′ data lines each (N=P×N′), each block receiving in parallelone of the P data signals which is demultiplexed on the N′ lines of thesaid block, characterized in that, alternately according to theselection lines, the scanning of the N′ data lines of a block is carriedout from 1 to N′ or from N′ to 1.

According to one embodiment of the present invention, the scan from 1 toN′ then from N′ to 1 is carried out every second selection line.

According to another embodiment which makes it possible to obtain thesame continuous level on all the columns, the scan from 1 to N′ thenfrom N′ to 1 is carried out for four successive selection lines, thescan being carried out in a first direction for two successive selectionlines and in a second direction for the other two succeeding selectionlines.

The present invention also relates to a circuit for implementing theabove process. This circuit consists of at least one programmable logiccircuit associated with a line counter determining the reversal of thedirection of scan.

BRIEF DESCRIPTION OF THE DRAWINGS

Other characteristics and advantages of the present invention willbecome apparent from reading the description given hereinbelow, thisdescription being given with reference to the drawings appended heretoin which:

FIG. 1 already described is a schematic representation of a matrixdisplay in which the columns are grouped into blocks, and which will beused for the implementation of the present invention.

FIG. 2, already described, represents the timing diagrams, over a linetime, of the odd numbered columns of a block DB consisting of 9 columns,and

FIG. 3 is a schematic representation of a circuit used to implement thepresent invention.

DETAILED DESCRIPTION

To simplify the description hereinbelow, in the figures the sameelements bear the same references.

The process in accordance with the present invention is applied chieflyto a matrix display of the type represented in FIG. 1. This displayconsists of N data lines or columns and M selection lines at theintersections of which are situated the image points or pixels (notrepresented). The N columns are grouped into P blocks 1 of N′ columnseach. By way of example, in FIG. 1 is represented a block of 9 columns.Usually for a screen used for a video display, the column controlcircuit will contain 80 blocks of 9 adjacent columns and will operatewith a sampling frequency of around 500 kHz. As represented in FIG. 1,each block 1 receives in parallel one of the P or 80 data signals whichis demultiplexed by the signals DW1 to DW9 on the N′ or 9 columns of ablock. In accordance with the present invention, to avoid the DC errorbetween the columns of one and the same block, due to the couplingbetween the gate of the sampling transistor and the column, which errorchanges as a function of the order of sampling of the columns, for theselection line L1, each block 1 is scanned successively from line C1 toC9 by applying sampling pulses DW1 to DW9, and signals such asrepresented in FIG. 2 are obtained on each column C1 to C9. Then, forthe next line L2 each block is scanned, beginning from column C9,towards column C1 by applying sampling pulses from DW9 to DW1 in such away as to reduce the DC error as explained in the introduction withreference to FIG. 2.

According to a variant embodiment of the process which makes it possibleto obtain the same continuous level on all the columns, the scan isreversed by reversing the arrival of the sampling pulses every secondline out of four lines according to the following table:

Line Frame 1 Frame 2 Frame 3 1 DW1 to 9 DW1 to 9 DW1 to 9 2 DW1 to 9 DW1to 9 DW1 to 9 3 DW9 to 1 DW9 to 1 DW9 to 1 4 DW9 to 1 DW9 to 1 DW9 to 15 DW1 to 9 DW1 to 9 DW1 to 9 6 DW1 to 9 DW1 to 9 DW1 to 9

It should be noted in the above table that, unlike what happens with thevideo data which are reversed on the image points from one frame toanother so as to avoid the marking of the cell, the direction ofscanning of the signals DWj is preserved from one frame to another for agiven selection line so as to avoid the AC error which would resulttherefrom.

The present invention also relates to a circuit making it possible toimplement this process. This circuit consists of at least oneprogrammable logic circuit associated with a line counter determiningthe reversal of the direction of scan.

An exemplary circuit making it possible to generate the scan of eachblock receiving the demultiplexing signals DW1 to DWN′ from 1 to N′ thenfrom N′ to 1 every 2 lines is represented in FIG. 3. This circuit isbased on a programmable logic circuit EPLD 10 which governs the order ofdispatch of the video data (DB) to the cell and the direction of scan ofthe signals DW (j=1 to N′) in a block receiving a given signal DB (i=1to P) according to the bit of rank 2 of the address at the output of theline counter (11) in the case of the example represented; that is tosay:

-   -   if the bit of rank 2 at the output of the line counter (11)        equals 0 (xxxxxx00 or xxxxxx01), the words DWj′ are read from 1        to N′ and the P video data, stored in the line memory 13, are        transferred to a D/A control circuit 14, i.e. a digital/analogue        converter upstream of the cell in the order of the DWs according        to the table below:

DW DB Column number 1 k N′ × (k − 1) + 1 with k integer and with kinteger and 1 ≦ k ≦ P 1 ≦ k ≦ P 2 k N′ × (k − 1) + 2 with k integer andwith k integer and 1 ≦ k ≦ P 1 ≦ k ≦ P N′ k N′ × (k − 1) + N′ with kinteger and with k integer and 1 ≦ k ≦ P 1 ≦ k ≦ P

-   -   otherwise the words DWj are read from N′ to 1 and the P video        data are transferred to the D/A control circuit 14 in the order        indicated in the table below:

DW DB Column number N′ k N′ × (k − 1) + N′ with k integer and with kinteger and 1 ≦ k ≦ P 1 ≦ k ≦ P 2 k N′ × (k − 1) + 2 with k integer andwith k integer and 1 ≦ k ≦ P 1 ≦ k ≦ P 1 k N′ × (k − 1) + 1 with kinteger and with k integer and 1 ≦ k ≦ P 1 ≦ k ≦ P

In more detail, the signal referenced Preset at the output of the linecounter 11 controlled by the line clock CL is dispatched respectively toa counter modulo N′ 15 and to a counter DW 16. The counter modulo N′ 15is controlled by the data clock CD and operates so that:

If Preset = 0 the video data are transferred as they are. If Preset ≠ 0N′ + 1 - the video data are transferred.

Likewise, the counter DW 16 is controlled by the clock of the DWs DWCand operates as follows:

If Preset = 0 the words are transferred in the normal order. If Preset ≠0 the words are transferred in the reverse order.

This cue at the output of the counter DW is dispatched to a levelshifting circuit 17 and returned to the counter modulo N′ 15.

It is obvious to the person skilled in the art that this is merely oneparticular embodiment which can be modified without departing from theclaims.

1. Process for displaying data on a matrix display having N data linesand P selection lines at the intersections of which are situated theimage points or pixels, and in which the N data lines are grouped into Pblocks of N′ data lines each (N=P×N′), each block receiving in parallelone of the P data signals which is demultiplexed on the N′ lines of saidblock, wherein, alternately, according to the selection lines, thescanning of the N′ data lines of a block is carried out from 1 to N′ andfrom N′ to 1, wherein a scanning direction is controlled as a functionof the selection line to provide a temporal average of a column. 2.Process according to claim 1, wherein the scan from 1 to N′ then from N′to 1 is carried out every second selection line, the scan being carriedout in a first direction for a first selection line and in a seconddirection for a succeeding selection line.
 3. Process according to claim1, characterized in that the scan from 1 to N′ then from N′ to 1 iscarried out for four successive selection lines, the scan being carriedout in a first direction for two successive selection lines and in asecond direction for the other two succeeding selection lines. 4.Circuit for implementing the process according to any one of claims 1 to3, characterized in that it consists of at least one programmable logiccircuit associated with a line counter determining the reversal of thedirection of scan.